Semiconductor packages and methods of manufacturing the same

ABSTRACT

Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 of Korean Patent Application No. 2008-0006703, filed on Jan.22, 2008, the entire contents of which are hereby incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Exemplary embodiments disclosed herein relate to semiconductor packagesand methods of manufacturing the same, and more particularly, tosemiconductor packages including two kinds of pads to which differentkinds of external terminals are connected, and methods of manufacturingthe same.

2. Description of the Related Art

A trend in the recent electronics industry is to manufacture asemiconductor device economically which is small, light, speedy, highlyreliable, and highly efficient. One of the techniques which canmanufacture the recently innovated semiconductor devices aresemiconductor packaging techniques.

A recent application device of an integrated circuit requires a numberof I/O pins, but a number of I/O pins causes many problems with relationto a conventional wire bonding package. A wire bonding package needs anumber of pads to be formed around a semiconductor substrate. As thenumber of I/O pins increases, there is a limitation of a minimum bondpitch that occurs by a limited size of a substrate. Solder bump arrayshave been developed to increase a capacity of I/O pins.

As a need to increase the number of I/O pins continuously increases, thetechnology needs to combine a solder bump array technique with a wirebonding technique so as to provide a high capacity of I/O pins. However,some characteristics of materials used in each of the techniques areunfavorable to work with. Materials suitable for use as solder bumpshave poor characteristics of mechanical adhesion. Thus, a material likecopper, for example, is a good soldering material but is not wellselected for the use of a wire bonding, One reason it that copper easilyforms an oxide layer that provides a bad bonding characteristic.Aluminum is also suitable for wire bonding. However, with aluminum, anoxide layer is formed on the entire surface thereof and the oxide mustcertainly be removed to get a strong soldering combination. However,corrosive agents for removing the oxide layer are very strong, so thataluminum disposed under an oxide layer is also corroded.

Gold is essentially needed for wire bonding. However, gold disposed on asolder bump pad is easily diffused into adjacent copper or adjacentsolder and forms not only a void but also forms an undesiredintermetallic compound that is vulnerable to an impact. Therefore, astructure of a redistribution pattern applicable to both a formation ofa solder bump and wire bonding, and its manufacture may be required toalleviate the problems described above.

SUMMARY OF THE INVENTION

Some exemplary embodiments provide a semiconductor package. Thesemiconductor package may include a substrate including a chip pad, aredistributed line which is electrically connected to the chip pad andincludes an opening and an external terminal connection portion, and afirst external terminal connection pad which is disposed at the openingand electrically connected to the redistributed line.

Additional aspects and utilities of the present general inventiveconcept will be set forth in part in the description which follows and,in part, will be obvious from the description, or may be learned bypractice of the general inventive concept.

Embodiments of the present general inventive concept may also byachieved by providing a semiconductor package, including a substrateincluding a chip pad, a redistributed line which is electricallyconnected to the chip pad and includes an opening and an externalterminal connection portion, and a first external terminal connectionpad which is disposed at the opening and electrically connected to theredistributed line.

The redistributed line is divided into a first redistributed line and asecond redistributed line by the opening and the second redistributedline is connected to the first redistributed line.

The redistributed line is divided into a first redistributed line and asecond redistributed line by the opening and the second redistributedline is spaced apart from the first redistributed line. The firstexternal terminal connection pad is disposed between the firstredistributed line and the second redistributed line. A first barrierlayer is disposed between the first external terminal connection pad andthe redistributed line to prevent an ingredient included in theredistributed line from being diffused into the first externalconnection pad.

A second external terminal connection pad is disposed on theredistributed line and electrically connected to the redistributed line.A second barrier layer which is disposed between the second externalterminal connection pad and the redistributed line to prevent aningredient included in the redistributed line from being diffused intothe second external connection pad.

A lowest bottom surface of the first external terminal connection pad isat the same level with a lowest bottom surface of the second externalterminal connection pad.

One of a solder bump is electrically connected to the first externalterminal connection pad or a bonding wire is electrically connected tothe external terminal connection portion.

A passivation layer is disposed on the substrate and exposes a portionof the chip pad so that the redistributed line provides a path connectedto the chip pad, and an insulating layer is disposed on the passivationlayer and exposes a portion of the redistributed line so that a portionof the redistributed line is used as the external terminal connectionportion.

Exemplary embodiments of the present general inventive concept provide asemiconductor package that may include a first semiconductor packagethat includes a redistributed line including an external terminalconnection portion that is disposed on a first chip, a bump padelectrically connected to the redistributed line, a solder bumpconnected to the bump pad, a bonding wire connected to the externalterminal connection portion, a second semiconductor package including asecond chip electrically connected to the first semiconductor package ina flip chip type by the medium of the solder bump, and a printed circuitboard electrically connected to the first semiconductor package by themedium of the bonding wire. One of the first and second chips is amemory chip and the other is a logic chip.

The first semiconductor package may further include a barrier layerwhich is disposed between the bump pad and the redistributed line toprevent an ingredient included in the redistributed line from beingdiffused into the bump pad.

Some exemplary embodiments provide a method of manufacturing asemiconductor package including providing a substrate including apassivation layer exposing a chip pad, forming a first metal layer onthe passivation layer, the first metal layer being electricallyconnected to the chip pad, forming a redistributed line including anopening on the first metal layer, the opening electrically connected tothe chip pad and exposing a portion of the first metal layer, forming anexternal terminal connection pad on the redistributed line, the externalterminal connection pad to which a first external terminal beingconnected, and forming an insulating layer exposing a portion of theredistributed line so as to use the portion of the redistributed line asan external terminal connection portion to which a different kind of asecond external terminal is connected.

The opening divides the redistributed line into first and secondredistributed lines of a connected configuration or a separatedconfiguration. Forming the redistributed line includes forming a firstphotoresist pattern on the first metal layer, the first photoresistpattern exposing a portion of the first metal layer, forming first andsecond redistributed lines by plating a conductive layer including goldusing the exposed first metal layer as a seed metal and using the firstphotoresist pattern as a mask, and forming the opening exposing thefirst metal layer by removing the first photoresist pattern.

The external terminal connection pad includes forming a second metallayer on the redistributed line, forming a first external terminalconnection pad and a second external terminal connection pad on thesecond metal layer, and lowest bottom surfaces of the first and secondexternal terminal connection pads being even with each other, whereinthe first external terminal connection pad is formed on the firstredistributed line and the second external terminal connection pad isformed on the opening, and forming a first barrier layer disposedbetween the first external terminal connection pad and the firstredistributed line, and a second barrier layer disposed between secondexternal terminal connection pad and the first and second redistributedlines by selectively removing the second metal layer,

Forming the external terminal connection pad includes forming a secondphotoresist pattern on the redistributed line, the second photoresistpattern exposing the opening, and forming the external terminalconnection pad by plating a conductive layer using the first metal layerexposed by the opening as a seed metal and using the second photoresistpattern as a mask. A second metal layer is formed in the opening beforeforming the external connection pad, and the external terminalconnection pad is formed by plating a conductive layer using the secondmetal layer as a seed metal and using the second photoresist pattern asa mask.

Forming the external terminal connection pad includes forming theinsulating layer so that a space is formed between sides of theconductive layer and the insulating layer, and forming the externalterminal connection pad so that the space is filled by reflowing theconductive layer.

Exemplary embodiments of the present general inventive concept may alsobe achieved by providing a semiconductor package including a firstsemiconductor package that includes a plurality of redistributed linesincluding recessed portions and non-recessed portions, bump padsdisposed above the recessed portions and non-recessed portions, andsolder bumps connected only to the bump pads disposed over thenon-recessed portions of the redistributed lines.

Exemplary embodiments of the present general inventive concept may alsobe achieved by providing a semiconductor package including a substrateincluding a chip pad, a redistributed line electrically connected to thechip pad and includes an opening that divides a first redistributed linefrom a second redistributed line, a passivation layer disposed on thesubstrate, wherein thicknesses of the first and second redistributedlines are equal to a thickness of the passivation layer.

Exemplary embodiments of the present general inventive concept may alsobe achieved by providing a method of manufacturing a semiconductorpackage, forming a first metal layer on a passivation layer that exposesa chip pad, the first metal layer being electrically connected to thechip pad, and forming a redistributed line including an opening on thefirst metal layer, the opening dividing a first redistributed line froma second redistributed line such that thicknesses of a first distributedline and a second distributed line are equal to a thickness of thepassivation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and utilities of the present generalinventive concept will become apparent and more readily appreciated fromthe following description of the embodiments, taken in conjunction withthe accompanying drawings of which:

FIGS. 1A through 1K are cross-sectional views illustrating a method ofmanufacturing a semiconductor package according to an embodiment of thepresent general inventive concept.

FIGS. 2A through 2E are cross-sectional views illustrating a method ofmanufacturing a semiconductor package according to a another embodimentof the present general inventive concept.

FIGS. 3A and 3B are cross-sectional views illustrating a method ofmanufacturing a semiconductor package according to a another embodimentof the present general inventive concept.

FIGS. 4A and 4B are cross-sectional views illustrating a semiconductorpackage of a multi-chip structure according to some embodiments of thepresent general inventive concept.

FIG. 5 is a perspective view illustrating an example of an electronicdevice including a semiconductor package according to some embodimentsof the present general inventive concept.

FIG. 6A is a top plan view illustrating a portion of FIG. 1K.

FIGS. 6B and 6 c are top plan views illustrating an enlarged portion ofFIG. 6A.

FIG. 7 is a top plan view illustrating a portion of FIG. 2E.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present general inventive concept now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the present general inventive concept are illustrated.The present general inventive concept may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the present general inventive concept to thoseskilled in the art. In the drawings, the size and relative sizes oflayers and regions may be exaggerated for clarity. Like numbers refer tolike elements throughout.

FIGS. 1A through 1K are cross-sectional views illustrating a method ofmanufacturing a semiconductor package according to an embodiment of thepresent general inventive concept.

Referring to FIG. 1A, a substrate 101 including an integrated circuit(not illustrated) is provided. The substrate 101 may be a silicon wafer.A chip pad 104 (e.g., aluminum) which is electrically connected to theintegrated circuit and a passivation layer 106 including an opening 106a which exposes the chip pad 104 may be formed on the substrate 101. Aninsulating layer 102 may be further formed between the substrate 101 andthe passivation layer 106.

Referring to FIG. 1B, an insulating layer 108 may be selectively furtherformed on the passivation layer 106. The insulating layer 108 may beformed to cover only a portion of the opening 106 a so as to expose thechip pad 104. If the integrated circuit can be isolated from otherthings (e.g., a redistributed line layer formed subsequently) by onlythe passivation layer 106, the insulating layer 108 may not be formed.

Referring to FIG. 1C, a first metal layer 110 which is electricallyconnected to the chip pad 104 is formed on the passivation layer 106. Inthe case that the insulating layer 108 is selectively further formed,the first metal layer 110 is formed on the insulating layer 108. As oneexample, the first metal layer 110 may be formed by sputtering copper(Cu), titanium (Ti)/copper (Cu), chromium (Cr)/copper (Cu), nickel (Ni),titanium (Ti)/nickel (Ni), chromium (Cr)/nickel (Ni) or the like.

Referring to FIG. 1D, a photoresist pattern 112 is formed on the firstmetal layer 110. The photoresist pattern 112 may be used as a mask toform redistributed lines 114 a and 114 b which will be described in FIG.1E.

Referring to FIG. 1E, redistributed lines 114 a and 114 b are formed onthe first metal layer 110. The redistributed lines 114 a and 114 b maybe formed to be a structure that first and second redistributed lines114 a and 114 b are connected as illustrated in FIG. 6B or a structurethat first and second redistributed lines 114 a and 114 b are spacedapart from each other as illustrated in FIG. 6C. In the presentembodiment, for example, the redistributed lines may be described to bedivided into the first redistributed line 114 a and the secondredistributed line 114 b. However, this does not mean that the firstredistributed line 114 a and the second redistributed line 114 b arealways spaced apart from each other.

A portion of the first redistributed line 114 a may be recessed by theopening 106 a. The redistributed lines 114 a and 114 b may beelectrically connected to the chip pad 104 by the medium of the firstmetal layer 110. For example, the redistributed lines 114 a and 114 bmay be formed of gold (Au) or copper (Cu)/Nickel (Ni)/gold (AU), orother combination to contact a gold or other material wire asillustrated in FIG. 1J. The redistributed lines 114 a and 114 b may beformed using electroplating or other known processes. In the case offorming the redistributed lines 114 a and 114 b using an electroplatingprocess, the first metal layer 110 may be used as a seed metal layer.

Referring to FIG. 1F, the photoresist pattern 112 is removed. An opening140 exposing a portion of the first metal layer 110 is formed betweenthe first redistributed line 114 a and the second redistributed line 114b. A redistributed second bump pad (118 b of FIG. 1H) is formed in theopening 140.

Referring to FIG. 1G, a second metal layer 116 is formed covering theredistributed lines 114 a and 114 b and the first metal layer 110. Thesecond metal layer 116 surrounds a top surface and a side surface ofeach of the first and second redistributed lines 114 a and 114 b, andcovers the first metal layer 110 exposed by the removal of the firstphotoresist pattern 112. For example, the second metal layer 116 may beformed by sputtering copper (Cu), titanium (Ti)/copper (Cu), chromium(Cr)/copper (Cu), nickel (Ni), titanium (Ti)/nickel (Ni), chromium(Cr)/Nickel (Ni) or the like.

Referring to FIG. 1H, a photoresist pattern 117 is formed on the secondmetal layer 116. A first external terminal connection pad (i.e., a firstbump pad 118 a) is formed on the redistributed line 114 a and a secondexternal terminal connection pad (i.e., a second bump pad 118 b) isformed between the first redistributed line 114 a and the secondredistributed line 114 b by an electroplating using the photoresistpattern 117 as a mask. The first and second bump pads 118 a and 118 bmay be external terminal connection pads to which external terminals,such as solder bumps, may be connected. The first and second bump pads118 a and 118 b may be concurrently formed using solder or nickel, forexample. In the case that the first and second bump pads 118 a and 118 bare formed by an electroplating process, the second metal layer 116 maybe used as a seed metal layer.

Since the first bump pad 118 a is formed on a first recessed portion ofthe first redistributed line 114 a, a portion of the first bump pad 118a may also be recessed. Similarly, since the second bump pad 118 b isformed on the opening 140, a portion of the second bump pad 118 b may berecessed. A recessed portion of the first bump pad 118 a constitutes thelowest surface 119 of the first bump pad 118 a and a recessed portion ofthe second bump pad 118 b constitutes the lowest surface 120 of thesecond bump pad 118 b. It is preferable that a height of the lowestsurface 119 is equal to or similar to a height of the lowest surface120. The reason for this is that solder bumps (150 a, 150 b in FIG. 1K)which will be described later may have a same height relative to eachother, so that an electrical connection can be uniformly distributedthroughout the device. For example, a height of the lowest surface 119of the first bump pad 118 a can be equal to or similar to a height ofthe lowest surface 120 of the second bump pad 118 b by controlling theprocess of forming the respective surfaces such that a thickness of theredistributed lines 114 a and 114 b may be equal to a thickness of thepassivation layer 106.

Referring to FIG. 1I, the photoresist pattern 117 is removed. A portionof the second metal layer 116 illustrated in FIG. 1H, exposed by aremoval of the photoresist pattern 117, is also removed. The portion ofthe second metal layer 116 can be removed using the first and secondbump pads 118 a and 118 b as an etching mask. When a portion of thesecond metal layer 116 is removed, a portion of the first metal layer110 illustrated in FIG. 1H, exposed outside of or external to the firstand second redistributed lines 114 a and 114 b, may be also removed withthe second metal layer 116. The first metal layer 110 becomes a metallayer pattern 111 which is disposed under the first and secondredistributed lines 114 a and 114 b by the removal of the portion of thefirst metal layer 110.

As further illustrated in FIG. 1I, by the removal of the outside orexternal portion of the second metal layer 116, the remaining portionsof the second metal layer 116 become a metal layer pattern 116 a that isdisposed between the first bump pad 118 a and the first redistributedline 114 a, and a metal layer pattern 116 b that is disposed between thesecond bump pad 118 b and the second redistributed line 114 b.

The metal layer pattern 116 a may function as a barrier layer preventingan ingredient (e.g., gold) included in the first redistributed line 114a from being diffused into the first bump pad 118 a when the layersundergo an annealing or other type of heating or other process thatcould cause diffusion of gold or any other metal. The metal layerpattern 111 may also act as a barrier layer preventing an ingredient inthe first redistributed line 114 a or the second redistributed line fromdiffusing into the lower layers of the semiconductor device. If themetal layer pattern 116 a is not present, an ingredient (e.g., gold)included in the first redistributed line 114 a diffuses into the firstbump pad 118 a to form a void in first bump pad 118 a and/or forms anundesired intermetallic compound in an interface between the first bumppad 118 a and the first redistributed line 114 a. The first bump pad 118a may be vulnerable to a negative impact due to a formation of anintermetallic compound. However, since the metal layer pattern 116 afunctions as a diffusion barrier, the phenomenon described above doesnot occur. Similarly, the metal layer pattern 116 b may function as abarrier layer preventing an ingredient (e.g., gold) included in thefirst and second redistributed lines 114 a and 114 b from being diffusedinto the second bump pad 118 b.

Referring to FIG. 1J, an insulating layer 130 including openings whichexpose portions of the first and second bump pads 118 a and 118 b, andthe second redistributed line 114 b is formed. The insulating layer 130may be formed by a process of depositing an insulating material, areflow process and a curing process, or other known processes. Theinsulating layer 130 is formed with a hole 141 that may expose a regionon the second redistributed line 114 b that may function as an externalterminal connection portion 142 (e.g., a bonding pad to which a goldwire is connected). Thus, a semiconductor package 100 including firstand second bump pads 118 a and 118 b, and the bonding pad 142 where abonding wire (illustrated in FIG. 1K) such as a gold is connected, maybe provided.

Referring to FIG. 1K, a first solder bump 150 a connected to the firstbump pad 118 a and a second solder bump 150 b connected to the secondbump pad 118 b may be selectively formed. As described above, since thelowest surface 119 of the first bump pad 118 a and the lowest surface120 of the second bump pad 118 b have a same or a similar heightrelative to each other, the first and second solder bumps 150 a and 150b, if formed to be substantially a same size, may have a same height ora similar height relative to each other as well. Thus, in the case whena semiconductor package 100 is electrically connected to a separatesemiconductor chip or a separate semiconductor package, the electricalconnections between adjacent chips or packages can be uniform. That is,when the semiconductor package 100 is attached to another semiconductorchip or package, a level and uniform physical package is created thatcan be more easily mounted on printed circuit boards (PCBs) and otherexternal devices. This uniform and level arrangement allows the packageas a whole to be made thinner as well as allows other semiconductorchips or packages to be formed on top of the semiconductor package 100more compactly, therefore enhancing the versatility and functionality ofthe semiconductor package 100 and overall package structure. The secondredistributed line 114 b may be used as a bonding pad 142 where abonding wire 160 is bonded thereto. Thus, the bonding wire 160 may beconnected to the semiconductor package 100 along with the first andsecond solder bumps 150 a and 150 b.

FIG. 6A is a top plan view depicting a portion of FIG. 1K and FIGS. 6Band 6C are top plan views enlarging a portion of FIG. 6A.

Referring to FIG. 6A, the redistributed lines 114 a and 114 b beingelectrically connected to the chip pad 104 is provided. The first bumppad 118 a where the first solder bump 150 a is connected is provided onthe first redistributed line 114 a and the second bump pad 118 b wherethe second solder bump 150 b is connected is provided between the firstand second redistributed lines 114 a and 114 b. The region of the secondredistributed line 114 b exposed through the hole 141 in the insulatinglayer 130 may function as a bonding pad 142 where a bonding wire 160 isconnected.

Referring to FIG. 6B, as described with reference to FIGS. 1E, 1F and6A, the redistributed lines 114 a and 114 b may be formed to have acontinuous connected structure surrounding the opening 140. As anexample embodiment, as described with reference to FIG. 1F, the opening140 formed by removing the photoresist pattern 112 may take the place ofa portion of a width of the redistributed lines 114 a and 114 b. Thus,the redistributed lines 114 a and 114 b may remain electricallyconnected to one another, with electrical current or signals passingaround the opening 140.

Referring to FIG. 6C, as another example embodiment, the opening 140 maysever the connection between the first and second redistributed lines114 a and 114 b. Thus, the redistributed lines 114 a and 114 b may bedivided into the first redistributed 114 a and the second redistributedline 114 b. This configuration allows for enhanced versatility of thesemiconductor package 100, in that electrical connections between thefirst and second redistributed lines 114 a and 114 b, respectively, maybe isolated.

FIGS. 2A through 2E are cross-sectional views illustrating a method ofmanufacturing a semiconductor package according to another embodiment ofthe present general inventive concept. Since the previous embodiment issimilar to the present embodiment, the description of common featuresalready discussed in the previous embodiment will be omitted forbrevity, while any new or different features will be described infurther detail below. Similar features to the previous embodimentinclude a substrate 201, a first insulating layer 202, a passivationlayer 206, and a second insulation layer 208.

Referring to FIG. 2A, a first redistributed line 214 a and a secondredistributed line 214 b including an opening 240 exposing a portion ofa first metal layer 210 are formed. For example, the first metal layer210 may be formed by sputtering copper (Cu), titanium (Ti)/copper (Cu),chromium (Cr)/copper (Cu), nickel (Ni), titanium (Ti)/nickel (Ni),chromium (Cr)/nickel (Ni) or the like.

Referring to FIG. 2B, a photoresist pattern 217 is formed. Thephotoresist pattern 217 under which the opening 240 exists is opened. Abump pad 218 is formed in the opening 240 using the photoresist pattern217 as a mask. The bump pad 218 may be formed by plating a solder ornickel using an electroplating. In this case, the first metal layer 210may be used as a seed metal.

Before forming the bump pad 218, a second metal layer 216 may be furtherformed. For example, the second metal layer 216 may be formed bysputtering copper (Cu), titanium (Ti)/copper (Cu), chromium (Cr)/copper(Cu), nickel (Ni), titanium (Ti)/nickel (Ni), chromium (Cr)/nickel (Ni)or the like. The bump pad 218 may be formed by an electroplatingprocess. The second metal layer 216 may be used as barrier layerpreventing an ingredient (e.g., gold) included in the first and secondredistributed lines 214 a and 214 b from being diffused into the bumppad 218 when annealing, other heat treatment, or other process isconducted that could cause diffusion. The first metal layer 210 alsoacts as a barrier layer against diffusion for gold or other metal layersdiffusing in another direction. When the bump pad 218 is formed byelectroplating, the second metal layer 216 may be used as a seed metal.

Referring to FIG. 2C, the photoresist pattern 217 is removed and thefirst metal layer 210 illustrated in FIG. 2B exposed by a removal of thephotoresist pattern 217 is etched. In this case, the first and secondredistributed lines 214 a and 214 b may be used as an etching mask toetch the first metal layer 210. The first metal layer 210 becomes ametal layer pattern 211 which is disposed under the first and secondredistributed lines 214 a and 214 b by the removal of the portion of thefirst metal layer 210.

Referring to FIG. 2D, an insulating layer 230 is formed. The insulatinglayer 230 is formed to allow the bump pad 218 and a portion of thesecond redistributed line 214 b exist to be exposed. A region where aportion of the redistributed line 214 b is exposed may function as abonding pad 242 to which a gold or other material wire may be bonded.Thus, a semiconductor package 200 of an embodiment of the presentgeneral inventive concept including a bump pad to which a solder bumpmay be connected and a wire bonding pad to which a gold wire may bebonded may be embodied through a series of the processes describedabove.

Referring to FIG. 2E, a solder bump 250 may be further formed on thebump pad 218 selectively, or by a number of known processes. In thesemiconductor package 200, the second redistributed line 214 b mayfunction as a bonding pad 242 to which a bonding wire 260 is bonded asdescribed above. Thus, the bonding wire 260 may be connected to thesemiconductor package 200 together with the solder bump 250.

FIG. 7 is a top plan view depicting a portion of FIG. 2E.

Referring to FIG. 7, through a series of the processes described above,for example, the redistributed lines 214 a and 214 b that areelectrically connected to the chip pad 204 are provided and the bump pad218 to which a solder bump is connected is provided between the firstredistributed line 214 a and the second redistributed line 214 b. Aportion of the second redistributed line 214 b may function as a bondingpad 242 to which the bonding wire 260 is connected.

The redistributed lines 214 a and 214 b, as illustrated in FIG. 6B, maybe formed to have a continuous connected structure. Alternatively, theredistributed lines 214 a and 214 b, as illustrated in FIG. 6C, may beformed to have a separated structure divided into a first redistributedline 214 a and a second redistributed line 214 b by the opening 240.

Referring to FIG. 3A according to yet another embodiment, an insulatinglayer 230 is formed. The insulating layer 230 is formed to allow a bumppad 218 and a portion of second redistributed line 214 b to be exposedas described with reference to FIG. 2D, but in this case the insulatinglayer 230 is not in contact with the bump pad 218. In this case, spaces230 a may be formed on one or both sides of the bump pad 218 and theinsulating layer 230.

Referring to FIG. 3B, the bump pad may be reflowed so that the space 230a is filled with a plated solder or nickel. After reflow, the outeredges of the bump pad 218 make direct contact with the redistributedlines 214 a and 214 b. Therefore the insulating layer 230 is in contactwith the redistributed lines 214 a and 214 b, but not in contact withthe barrier layer 216. Thus, as described with reference to FIG. 2D, asemiconductor package having different pads 218 and 242 is embodied.

FIGS. 4A and 4B are cross-sectional views of a semiconductor package ofa multi-chip structure according to example embodiments of the presentgeneral inventive concept.

Referring to FIG. 4A, in a multi-chip package 1000 such as a chip onchip, a semiconductor package 100 of the embodiment of FIG. 1K, forexample, is mounted on a top surface of a printed circuit board 180 sothat the semiconductor package 100 is electrically connected to theprinted circuit board 180 by the medium of a bonding wire 160. Adifferent kind of a semiconductor package 170 may be mounted on thesemiconductor package 100 in a flip chip type so that the different kindof a semiconductor package 170 is electrically connected to thesemiconductor package 100 by the medium of a plurality of solder bumps150 a and 150 b. The semiconductor packages 100 and 170 may be a packageof a chip unit. A molding layer 190 sealing up the semiconductorpackages 100 and 170 may be formed on a top surface of the printedcircuit board 180 and a plurality of solder balls 195 which areterminals for external connection are adhered to a bottom surface of theprinted circuit board 180. The semiconductor packages 100 and 170 mayinclude different chips. For instance, the semiconductor package 100 mayinclude a memory chip and the semiconductor package 170 may include alogic chip, for example.

As described with reference to FIGS. 1A through 1K, the semiconductorpackage 100 may include different external terminals (e.g., bump pads118 a and 118 b and a bonding pad 142 to which solder bumps 150 a and150 b and a bonding wire 160 are adhered, respectively.

Referring to FIG. 4B, in a multi-chip package 2000 such as a chip onchip package, the semiconductor package 200 of the embodimentillustrated in FIG. 2E, for example, is electrically connected to asemiconductor die or chip 170 by the medium of a plurality of solderbumps 250 and is electrically connected to a printed circuit board by abonding wire 260. FIG. 4B also illustrates a configuration where not allof the possible electrical connections are established between thesemiconductor package 200 and the semiconductor package 170. Forexample, the recessed redistribution lines 214 a are unconnected tosolder bumps, but the bump pads 218 that are disposed above non-recessedportions of the redistributed lines are connected to solder bumps 250.By connecting the different solder bumps of the semiconductor package indifferent configurations, the versatility of the entire packagingstructure is enhanced. Similarly, different size semiconductor dies andchips can be used in combination with the semiconductor package 200, toincrease the functionality of the present general inventive concept.

FIG. 5 is a perspective view of an example of an electronic deviceincluding a semiconductor package according to some embodiments of thepresent general inventive concept.

Referring to FIG. 5, the semiconductor packages 100, 200, 1000 and 2000described according to embodiments of the present general inventiveconcept may be used in an electronic device 3000 such as a note bookcomputer. The electronic device 3000 may include a desk top computer, acamcorder, a mobile phone, a game player, a portable multimedia player(PMP), a MP3P player, a liquid crystal display, a plasma display (PDP),a memory card or the like. Particularly, since the electronic device mayinclude a semiconductor device including different pads, a reliableelectrical connection to a diverse amount different chips with varyingfunctionalities can be embodied.

Although a few embodiments of the present general inventive concept havebeen illustrated and described, it will be appreciated by those skilledin the art that changes may be made in these embodiments withoutdeparting from the principles and spirit of the general inventiveconcept, the scope of which is defined in the appended claims and theirequivalents.

1. A semiconductor package, comprising: a substrate including a chippad; a redistributed line which is electrically connected to the chippad and includes an opening and an external terminal connection portion;and a first external terminal connection pad which is disposed at theopening and electrically connected to the redistributed line.
 2. Thesemiconductor package of claim 1, wherein the redistributed line isdivided into a first redistributed line and a second redistributed lineby the opening and the second redistributed line is connected to thefirst redistributed line.
 3. The semiconductor package of claim 1,wherein the redistributed line is divided into a first redistributedline and a second redistributed line by the opening and the secondredistributed line is spaced apart from the first redistributed line. 4.The semiconductor package of claim 3, wherein the first externalterminal connection pad is disposed between the first redistributed lineand the second redistributed line.
 5. The semiconductor package of claim4, further comprising: a first barrier layer which is disposed betweenthe first external terminal connection pad and the redistributed line toprevent an ingredient included in the redistributed line from beingdiffused into the first external connection pad.
 6. The semiconductorpackage of claim 4, further comprising: a second external terminalconnection pad which is disposed on the redistributed line andelectrically connected to the redistributed line.
 7. The semiconductorpackage of claim 6, further comprising: a second barrier layer which isdisposed between the second external terminal connection pad and theredistributed line to prevent an ingredient included in theredistributed line from being diffused into the second externalconnection pad.
 8. The semiconductor package of claim 6, wherein alowest bottom surface of the first external terminal connection pad isat the same level with a lowest bottom surface of the second externalterminal connection pad.
 9. The semiconductor package of claim 1,further comprising: one of a solder bump electrically connected to thefirst external terminal connection pad and a bonding wire electricallyconnected to the external terminal connection portion.
 10. Thesemiconductor package of claim 1, further comprising: a passivationlayer which is disposed on the substrate and exposes a portion of thechip pad so that the redistributed line provides a path connected to thechip pad; and an insulating layer which is disposed on the passivationlayer and exposes a portion of the redistributed line so that a portionof the redistributed line is used as the external terminal connectionportion.
 11. A semiconductor package, comprising: a first semiconductorpackage that includes a redistributed line including an externalterminal connection portion that is disposed on a first chip; a bump padelectrically connected to the redistributed line, the bump pad to whicha solder bump being connected, and a bonding wire connected to theexternal terminal connection portion; a second semiconductor packageincluding a second chip electrically connected to the firstsemiconductor package in a flip chip type by the medium of the solderbump; and a printed circuit board electrically connected to the firstsemiconductor package by the medium of the bonding wire.
 12. The ofsemiconductor package claim 11, wherein one of the first and secondchips is a memory chip and the other is a logic chip.
 13. Thesemiconductor package of claim 11, wherein the first semiconductorpackage further comprises a barrier layer which is disposed between thebump pad and the redistributed line to prevent an ingredient included inthe redistributed line from being diffused into the bump pad. 14-20.(canceled)
 21. The semiconductor package of claim 1, comprising: abarrier layer disposed between the redistributed line and the firstexternal terminal connection pad; and an insulating layer in contactwith the redistributed line and the first external terminal, but not incontact with the barrier layer.
 22. A semiconductor package, comprising:a first semiconductor package that includes a plurality of redistributedlines including recessed portions and non-recessed portions; bump padsdisposed above the recessed portions and non-recessed portions; andsolder bumps connected only to the bump pads disposed over thenon-recessed portions of the redistributed lines.
 23. A semiconductorpackage, comprising: a substrate including a chip pad; a redistributedline electrically connected to the chip pad and including an openingthat divides a first redistributed line from a second redistributedline; a passivation layer disposed on the substrate, wherein thicknessesof the first and second redistributed lines are equal to a thickness ofthe passivation layer.
 24. (canceled)